1. Technical Field
This disclosure relates generally to drivers, and more particularly, but not exclusively, relates to low voltage differential signaling devices.
2. Background Art
Various high speed differential serial link standards have been designed to accommodate increased off-chip data rate communications. High speed Universal Serial Bus (USB), firewire (IEEE-1394), serial Advanced Technology Attachment (ATA) and Small Computer System Interface (SCSI) are a few of the standards used for serial data transmission in the PC industry. Low voltage differential signaling (LVDS) has also been implemented in transmission-side serial data communications.
Additionally, vendors (such as cellular phone companies) have proposed a “subLVDS” standard, which is a smaller voltage-swing variant of the LVDS standard. SubLVDS has been suggested for use in the Compact Camera Port 2 (CCP2) specification for serial communications—e.g. between image sensors and onboard systems.
CCP2 is part of the Standard Mobile Imaging Architecture (SMIA) standard. Typical LVDS/subLVDS levels have an output common mode level (Vcm) between supply voltages VDD and VSS. For example, transmitters (Tx) for CCP2 normally have an output signal swing (Vod) of 150 mV with center voltage Vcm at 0.9V.
In addition to high speed image data, low speed chip control signals are often transmitted between host and client. Several new protocols have been developed for high speed (“HS”) to low power (“LP”) state changes using common mode levels. A joint effort among various cellular phone companies has defined a new physical layer (PHY) standard. The PHY standard defines the Mobile Industry Processor Interface (MIPI), which combines high speed image data transmission and low speed control signals in a single communication signal path (“lane”).
FIG. 1 is a block diagram showing a conventional LVDS interface 100. LVDS interface 100 includes a differential current switch pair 101 for a driver (or “output”) stage with a current source 102. The tail current from differential current switch pair 101 is adjusted to control the output voltage swing. The common mode level Vcm is sensed by tapping the mid-point of back termination resistor 103. The Vcm is tracked and adjusted using common mode feedback filter 104 in real time.
For high speed transmission, a certain degree of impedance matching has been used for longer transmission lines. A conventional LVDS interface typically includes 100Ω to 200Ω back termination resistor 103 on chip between differential output pads Dp and Dn—e.g. to improve differential reflection coefficients lower than −10 dB at frequencies of typical interest. However, real time Vcm tracking in such a design is not realistic due to the longer common mode settle times required during a mode change from LP to HS mode—e.g. from a logic high voltage of 1.2V in LP mode to logic high voltage of 100 mV in HS mode. Also, a power penalty may result from back termination resistors 103, which could result in a need for an additional 50% to 100% for output driver current. Therefore, low common mode transmission designs exhibit limited responsiveness to LVDS settle times and/or limited efficiencies in silicon space or power consumption.